Integrated circuits are formed on wafers by well-known processes and materials. These processes typically include the deposition of thin film layers by sputtering, metal-organic decomposition, chemical vapor deposition, plasma vapor deposition, and other techniques. These layers are processed by a variety of well-known etching technologies and subsequent deposition steps to provide a completed integrated circuit.
A crucial component of integrated circuits is the wiring or metallization layer that interconnects the individual circuits. Conventional metal deposition techniques include physical vapor deposition, e.g., sputtering and evaporation, and chemical vapor deposition techniques. Some integrated circuit manufacturers are investigating electrodeposition techniques to deposit primary conductor films on semiconductor substrates.
Wiring layers traditionally contained aluminum and a plurality of other metal layers that are compatible with the aluminum. In 1997, IBM introduced technology that facilitated a transition from aluminum to copper wiring layers. This technology has demanded corresponding changes in process architecture towards damascene and dual damascene architecture, as well as new process technologies.
A typical damascene or dual damascene process flow scheme for fabricating copper interconnects, such as copper lines and vias, typically includes: forming a trench pattern on a layer dielectric layer using an etch-resistant photoresist; etch a trench pattern; remove the photoresist; forming a via pattern on a dielectric material using etch resistant photoresist; etching vias; removing resist; depositing a tantalum barrier and a copper seed layer using PVD; electroplating copper to fill the etched features; and polishing copper off the wafer face leaving copper-filled interconnect circuitry.
Copper damascene circuits are produced by initially forming trenches and other embedded features in a wafer, as needed for circuit architecture. These trenches and embedded features are formed by conventional photolithographic processes in a nonconductive substrate, such as a silicon oxide. A barrier layer, e.g., of silicon nitride or tantalum, is deposited next. An initial seed or strike layer typically comprising copper and having a thickness of about 20 nanometers (nm) to 200 nm is then deposited by a conventional physical or vapor deposition technique. The seed layer is used as a base layer to conduct current for electroplating thicker films. Thinner seed layers are preferred so as to reduce overhang and closure of very small features with metal from the seed layer. The seed layer functions as the cathode of an electroplating cell. Electrical contacts to the wafer are normally made at its edge. Since the seed layer is usually very thin, there is a significant resistive drop between the points of contact at the edge of the wafer and the center of the wafer. This is referred to as the “terminal effect”. When the system is operating in a regime in which the plating rate is determined by the magnitude of the current, the plating rate is greater at the edge of the wafer than at the center of the wafer. As a result, the plated layer often has a concave dish-shaped profile initially. As the thickness of the copper layer increases during plating, the terminal effect diminishes and the plated layer is deposited at a more uniform rate. U.S. Pat. No. 6,074,544, issued Jun. 13, 2000 to Reid et al., which is hereby incorporated by reference, teaches a method of electroplating on a semiconductor wafer using a low current density initially to reduce resistance drop between the edge of the wafer and the center of the wafer, and then increasing the current density after the metal layer has reached a predetermined thickness.
Generally, in electroplating processes, the thickness profile of the deposited metal is controlled to be as uniform as possible. This uniform profile is advantageous in subsequent etchback or polish removal steps, as well as uniform void-free filling of the trench structures. Prior art electroplating techniques are susceptible to thickness irregularities. Factors contributing to these irregularities include the size and shape of the electroplating cell, electrolyte depletion effects, hot edge effects, and the terminal effect.
Regarding the trend towards larger diameter wafers, it is generally understood that the deposition rate, as measured by layer thickness, can be maintained by scaling total current through the electrochemical reactor in proportion to the increased surface area of the larger wafer. Thus, a 300 millimeter (mm) wafer requires 2.25 times more current than does a 200 mm wafer. Electroplating operations are preferably performed by using a clamshell-type wafer holder that contacts the wafer only at its outer radius. Due to this mechanical arrangement, the total resistance from the edge of the wafer to the center of the wafer is proportional to the radius. Nevertheless, with the higher applied current at the edge of the larger wafer, which is required to maintain the same current density for process uniformity, the total potential drop from the edge to the center of the wafer is greater for the larger diameter wafer. This circumstance leads to an increased rate of deposition that increases with radius where deposition is measured by layer thickness. While the problem of increasing deposition rate with radius exists for all wafers, it is exacerbated in the case of larger wafers.
The introduction of damascene metallization for copper interconnects has led to the development and modification of processes for 0.13 microns (μm) and smaller design rules. The implementation of new process flows has caused new device-killing defect formation. In copper damascene metallization, defects generally arise during the three main process sequences: deposition of barrier and seed layers; electrofill operations, including pre- and post-anneal; and chemical mechanical polishing (CMP).
Critical post-plating in-film killer defects in electroplated copper layers include pits, craters, and voids, which typically form during the electroplating process or during the post-plate anneal steps. Another type of defect are single isolated protrusions. Single isolated protrusions can usually be eliminated during CMP.
A conventional electroplating bath typically contains the metal to be plated together with associated anions in an acidic solution. Copper electroplating is usually performed using CuSO4 and a chloride dissolved in an aqueous solution of sulfuric acid. In DC electroplating, additives such as accelerators, suppressors, and levelers are typically included in the electrolytic plating solution to improve electroplating behavior by, among others, enhancing chemical reactions, improving surface deposition, improving thickness uniformity, and enhancing filling of high aspect ratio features. Sulfuric acid provides high conductivity to the electrolyte, and chloride ions enhance additive performance.
Three types of electroplating bath additives are in common use, subject to design choice by those skilled in the art. A suppressor additive is used to decrease the current density, and thus the deposition rate on the surface of the wafer at a given applied voltage. This allows differentiation in deposition rate between the wafer surface and the inside of high aspect ratio features, thereby enhancing the void-free fill of high aspect ratio features. Typical suppressors are large molecules, typically having an average molecular weight (MW) in a range of about from 2,000 to 6,000, that increase the surface polarization layer and prevent copper ion from readily adsorbing onto the surface. Thus, suppressors function as blockers. Suppressors cause the resistance of the surface to be very high in relation to the electroplating bath. Trace levels of chloride or other ion may be required for suppressors to be effective.
Accelerator additives accumulate within the high aspect ratio features to increase the local current density relative to the suppressed field and thus aid in void free filling. Accelerator additives are normally catalysts that accelerate the plating reaction. Accelerators typically are rather small molecules (e.g., 300 MW) that normally contain sulphur, and they need not be ionic. Accelerators adsorb onto the surface and increase the flow of current. Accelerators may occur not as the species directly added to the electroplating bath, but as breakdown products of such molecules. In either case, the net effect of accelerators is to increase current flow and accelerate the reaction when such species are present or become present through chemical breakdown.
A leveler additive is present to improve overall deposit planarity and increase the ease of subsequent CMP processing. Levelers behave like suppressors, but tend to be more electrochemically active (i.e., are more easily electrochemically transformed) than suppressors. Levelers are typically consumed during electroplating. Levelers tend to supress plating on raised regions of the surface undergoing plating, thus, tending to level the plated surface.
In conventional electroplating solutions, the additive components were designed to provide ideal characteristics for bottom-up fill of trench and vias, as well as planarization of plating above filled features. The presence of additives and chloride ions in an electrolytic plating bath, however, often leads to occlusion of undesired material in the deposited metal layer. When a damascene or dual damascene process flow scheme is used with a conventional electroplating bath, under certain conditions of wafer entry, lines of pits may result on the wafer surface. Pit defects often result in void formation in vias and trenches and subsequent yield loss.
U.S. Pat. No. 6,113,771, issued Sep. 5, 2000, to Landau et al., teaches electroplating solutions that contain various additives introduced typically in small (ppm range) amounts useful, among other reasons, for improving wetting of the part being plated. Without mentioning their purpose, U.S. Pat. No. 6,113,771 mentions polyethylene glycols as a group of additives, and it specifically mentions a polyethylene-glycol additive having an average molecular weight of 1400, and a propylene glycol additive. U.S. Pat. No. 5,969,422, issued Oct. 19, 1999, to Ting et al., teaches an electroless deposition solution that may contain polyethylene glycol as a surfactant and wetting agent. U.S. patent application Publication No. 20020064592, published May 30, 2002, for Datta et al., teaches electroless copper deposition using an electroless bath in which polyethylene glycol (5–100 ppm), polypropylene glycol and other surfactants may be used as a wetting agent.